1. Field of the Invention
The present invention relates generally to dynamic random access memory devices, and more particularly, to a dynamic random access memory device having a self-refresh mode which automatically initiates a periodical refresh operation.
2. Background Art
In recent years, personal computers have been significantly used generally. In particular, recently, the demand for portable personal computers has been increased. Such a personal computer requires a memory device having low power consumption the power supply of which is backed up by a battery. As a memory device for such a use, a static random access memory or a dynamic random access memory (referred to as DRAM hereinafter) have been employed.
In the DRAM, each memory cell generally comprises a single transistor and a single capacitor. This is referred to as a so-called a single transistor/a single capacitor type memory cell, which is suitable for decrease in the area of a cell and high integration density.
FIG. 12 is a block diagram showing a conventional 1-megabit DRAM. In FIG. 12, this DRAM comprises memory arrays 21 to 24 each comprising a memory cell MC for storing a data signal, row decoders 11, column decoders 13 and sense amplifiers 12, each of the row decoders 11, each of the column decoders 13 and each of the sense amplifiers being connected to each of the memory arrays 21 to 24 to constitute each memory array block, a word line driving circuit 70 connected to each of the row decoders 11, a sense amplifier driving circuit 60 connected to each of the sense amplifiers 12, and pre-amplifiers 111 to 114 each for amplifying the data signal as read out. In addition, this DRAM is provided with a RAS buffer 101 receiving a row address strobe (referred to as RAS hereinafter) signal from the exterior, a CAS buffer 102 receiving a column address strobe (referred to as CAS hereinafter) signal, a row address buffer 104 for receiving row address signals RA.sub.0 to RA.sub.9, a column address buffer 105 for receiving column address signals CA.sub.0 to CA.sub.9, a write buffer 106 receiving a write control signal W, an input buffer 107 receiving an input data signal Din, and an output buffer 108 temporarily holding an output data signal Do. There is provided a refresh determining circuit 9a for determining a refresh mode between the RAS buffer 101 and the CAS buffer 102. The refresh determining circuit 9a has its output connected to a refresh control circuit 50a for controlling a refresh operation. An address counter 103 is provided for generating in the internal address signals Q.sub.0 to Q.sub.8 for refreshing.
Operations will be briefly described. First, the row and column address signals RA.sub.0 to RA.sub.9 and CA.sub.0 to CA.sub.9 are applied to this DRAM through an address input terminal. Each of the address signals is held in the row address buffer 104 and the column address buffer 105 in response to timings of the falling edges of the RAS and CAS signals. Then, a word line is selected in each of the row decoders 11 in response to the row address signals RA.sub.0 to RA.sub.8. A word line driving signal WL is outputted to each of the row decoders 11 from the word line driving circuit 70, so that the word line connected to the signal WL is activated.
Thereafter, for example, in a reading operation, a signal stored in the memory cell MC is applied to a bit line BLl. This signal is amplified by the sense amplifier 12 and then, selected by the column decoder 13, thereby to be applied to a read/write line I/0.sub.1. By the foregoing operations, signals read out from the four memory arrays 21 to 24 are respectively applied to write/read lines I/0.sub.1 to I/0.sub.4. The pre-amplifiers 111 to 114 further amplify the signals, respectively.
In a nibble mode, a nibble decoder 109 is operated as a shift register, so that a 4-bit data signal read out by toggling the CAS signal is sequentially transferred to the output buffer 108 through transistors Q.sub.51 to Q.sub.54 at high speed. In an ordinary mode excluding the nibble mode, the nibble decoder 109 is operated as a decoder for decoding most significant address signals RA.sub.9 and CA.sub.9, so that a data signal of one bit out of four bits is transferred to the output buffer 108 through the transistors Q.sub.51 to Q.sub.54 in response to the decoded signals.
Contrary to this, in a writing operation, the input data signal Din is written into the memory cells MC through the read/write lines I/0.sub.1 to I/0.sub.4.
FIG. 13A is a circuit diagram showing an example of a specific circuit in each of the memory array blocks shown in FIG. 12, and FIG. 13B is a timing chart for explaining the operation. The figures are described in Digest of Technical Papers of IEEE International Solid-State Circuits Conference held in 1985, pp. 252-253.
Referring to FIG. 13A, this memory array block comprises a memory array and a sense amplifier which handle a 256K-bit data signal. Therefore, there are provided 512 word lines WL1 to WL512 connected to a row decoder, 512 bit line pairs BL1 and BL1 to BL512 and BL512 each connected to the sense amplifier 2 being provided in a direction intersecting therewith. In addition, output lines Y1 to Y512 of a column decoder are connected to each column.
For example, in a column 5 including the bit lines BLl and BLl, a memory cell MC is connected between the bit line BLl and the word line WL1. The memory cell MC comprises an NMOS transistor Q.sub.0 for switching and a capacitor C.sub.0 for storing a signal. The capacitor C.sub.0 has one electrode connected to receive a constant voltage Vcp (for example, a voltage of one-half of a power-supply voltage Vcc) generated within a chip. The sense amplifier 2 comprises an N channel flip-flop comprising NMOS transistors Q.sub.1 and Q.sub.2 and a P channel flip-flop comprising PMOS transistors Q.sub.3 and Q.sub.4. The transistors Q.sub.3 and Q.sub.4 have their sources integrally connected to a common source line SP, and the transistors Q.sub.1 and Q.sub.2 have their sources integrally connected to a common source line SN. A gate circuit 3 comprises NMOS transistors Q.sub.5 and Q.sub.6 each connected between the bit lines BL1 and BL1 and lines I/0 and I/0. The transistors Q.sub.5 and Q.sub.6 have their gates connected to the output line Y1 of the column decoder. A bit line equalizing and holding circuit 4 comprises NMOS transistors Q.sub.7 to Q.sub.9 integrally connected to each other such that gates thereof receive an equalize signal EQ. The bit lines BLl and BL1 are connected to receive a bit line precharging voltage V.sub.BL (1/2Vcc) through this circuit 4. When the RAS signal is at a high level (in a standby state), the voltage V.sub.BL is applied to the bit lines BLl and BL1.
There are provided a total of 512 columns 5 of various circuits connected to the above described bit line pair. In the above described manner, a total of 262, 144-bit (256K) memory array blocks are structured.
A sense amplifier activating circuit 6 comprises a PMOS transistor Q.sub.11 connected between a power supply Vcc and a common source line SP and an NMOS transistor Q.sub.10 connected between ground and a common source line SN. The transistors Q.sub.10 and Q.sub.11 have their gates respectively connected to receive signals So and So from the sense amplifier driving circuit 60.
Referring now to FIGS. 13A and 13B, operations will be described.
The equalize signal EQ is almost synchronized with the external RAS signal. This signal EQ is at a high level before a time tl, so that the DRAM is brought to a state in which the RAS signal is at a high level, i.e., a standby state. In this state, the transistors Q.sub.7 to Q.sub.9 are turned on, so that all the bit line pairs BLl to BL512 are brought to 1/2 Vcc. One of the bit line pair is brought to a power-supply Vcc level and the other thereof is brought to a ground level in the previous operation cycle and then, the transistor Q.sub.7 is turned on at the time of determination of the cycle, so that this voltage becomes 1/2 Vcc. Thus, a voltage of 1/2 Vcc need not be supplied from the power supply V.sub.BL. However, when the standby state lasts for a long time, the voltage V.sub.BL is supplied for the purpose of preventing a voltage on the bit line pair from being fluctuated by some noises. More specifically, the voltage V.sub.BL is applied to the bit line pair through the transistors Q.sub.8 and Q.sub.9 in order to hold the bit line pair at a V.sub.BL level rather than to supply the voltage to the bit line pair.
First, in the reading operation, at about a time tl, the RAS signal is changed to a low level, and the signal EQ is also changed to a low level. The transistors Q.sub.7 to Q.sub.9 are turned off in response to the signal EQ, so that the bit line pair BL1 and BL1 is rendered electrically floating. On the other hand, at this time, the row address signals to RA.sub.0 to RA.sub.9 are inputted at timings of the falling edge of the RAS signal as described above. The row decoder decodes the signals RA.sub.0 to R.sub.8, to bring one (for example, WL1) out of 512 word lines WL1 to WL512 into a high level. As shown in FIG. 13A, a total of 512 memory cells each connected to either one of the two bit lines for each column are connected to the word line WL1. The word line WL1 is brought to a high level, so that the transistor Q.sub.0 is turned on, whereby a signal stored in each of the memory cells is applied to a bit line. Since the ratio of a capacitance value of the capacitor C.sub.0 in the memory cell to a capacitance value of the bit line is approximately 1:10, the change in voltage of approximately one-tenth of the power-supply voltage Vcc appears on the bit line. For example, as shown in FIG. 3A, a voltage on the bit line BLl is slightly raised. On the other hand, a voltage of the bit line BL1 remains at 1/2 Vcc.
At a time t3, the sense amplifier driving signals So and So are respectively changed to a high level and a low level. The transistors Q.sub.10 and Q.sub.11 are turned on in response to the signals, so that the 512 sense amplifiers 2 are driven. Thus, for example, a very small change in voltage which slightly appeared between the bit lines BLl and BL1 is amplified, so that the bit line BLl is brought to a high level while the bit line BL1 is brought to a low level. At this time point, voltages of the 512 bit line pairs are changed by the 512 sense amplifiers in response to the data signals stored in the 512 memory cells.
At a time t4, an output signal (for example, a high level signal Y1) for selecting one of the 512 bit line pairs is outputted from the column decoder. The transistors Q.sub.5 and Q.sub.6 are turned on in response to the signal Y1, so that the amplified data signal is applied to the read/write line pair I/0 and I/0. This read/write line pair has been brought to a floating state in advance, the level thereof being changed depending on the level of the signal from the bit line pair.
At a time t5, a voltage of the word line WL1 is changed to a low level, so that each of the memory cells connected to this word line WL1 and each of the bit lines are electrically disconnected. In addition, at a time t6, the sense amplifier driving signals So and So are respectively changed to a low level and a high level, so that the equalize signal EQ is changed to a high level. Consequently, all the bit line pairs are brought to a 1/2 Vcc level, so that the DRAM is brought to a standby state in preparation for the next cycle. In the foregoing, one operation cycle is terminated.
Meanwhile, the level of voltages of bit lines amplified in a period from the time t3 to time t5 is rewritten to all the memory cells connected to the word line WL1 by the voltages thereof. In addition, the change in voltage represented by a dotted line in FIG. 13B corresponds to a case in which a data signal of a level opposite to that in the above described case is stored in a memory cell.
Then, in the writing operation, the read/write line pair I/0 and I/0 is brought to the level of a data signal to be written in response to the input data signal inputted to the input buffer 107. This data signal is applied to a bit line pair selected by the column decoder after the time t4, to be stored in a memory cell connected to a word line which was brought to a high level.
FIG. 13C is a cross sectional view showing a structure of a planar capacitor type memory cell employed in the conventional DRAM. Referring to FIG. 13C, an NMOS transistor Q.sub.0 and a capacitor C.sub.0 for constituting a memory cell are formed on a P-type semiconductor substrate 301. The transistor Q.sub.0 has its source and drain formed in N.sup.+ impurity regions 304 and 305 provided in the substrate 301. The transistor Q.sub.0 has its gate 308 formed on the substrate 301 through an insulating film 306. The capacitor C.sub.0 has one electrode formed of an impurity diffused layer 303 formed in the vicinity of a main surface of the substrate 301 and another electrode formed of a cell plate 307 of polysilicon (polycrystalline silicon) provided on the layer 303 through an insulating film 312. An insulating film 302 is provided for isolating adjacent memory cells. An N.sup.+ impurity region 305 is connected to a bit line (not shown) of polysilicon, and the gate 308 is connected to a word line (not shown) of polysilicon.
A data signal to be stored in a memory cell is held in the capacitor C.sub.0. More specifically, signal charges are charged between the impurity diffused layer 303 and the cell plate 307 by the data signal. However, a leak current flows into the substrate 301 from a junction of the layer 303, the region 304 and the substrate 301, so that the charged signal charges are liable to be gradually lost. This current is referred to as a junction leak current.
The refresh operation will be described.
A memory cell in the DRAM comprises a single transistor and a single capacitor, as described above. Thus, for example, if the DRAM continues to be brought into a standby state for a long time, charges for storing stored in the capacitor are gradually lost by junction leak or the like, as described above. Therefore, stored signals must be read out every given constant time period, to be rewritten. The operation is referred to as refreshing. A mode for executing the refresh operation generally includes the following two modes. First, in a RAS only refresh mode, the RAS signal and the row address signal are applied from the exterior, so that the refresh operation is performed. Then, in a CAS before RAS (auto) refresh mode, only RAS and CAS signals are applied from the exterior, so that the refresh operation is performed using a signal outputted from an address counter in the interior. In the following description, the refresh modes are referred to as an ordinary refresh mode.
The CAS before RAS refresh operation will be described. When the ordinary reading or writing operation is initiated, it is determined that the RAS signal is lowered and then, the CAS signal is lowered. On the contrary, when the CAS signal is lowered prior to the RAS signal, this CAS before RAS refresh mode is initiated. In order to detect timings at which the RAS and CAS signals are changed, there is provided the refresh determining circuit 9a shown in FIG. 12. When designation of the CAS before RAS refresh mode is detected by the circuit 9a, the refresh control circuit 50a initiates an operation of the address counter 103. In addition, the row address buffer 104 receives the signals Q.sub.0 to Q.sub.8 outputted from the address counter 103 in place of the address signals A.sub.0 to A.sub.9 externally applied, in response to a signal from the control circuit 50a. The row address signals RA.sub.0 to Ra.sub.8 for refreshing are outputted from the row address buffer 104. The subsequent operations are almost the same as the above described reading operation except that a data signal read out to a bit line pair is not applied to a read/write line pair.
More specifically, returning to FIG. 13A, one of the 512 word lines is selected, so that the 512 memory cells are connected to the 512 bit line pairs. A data signal applied to each of the bit line pairs from each of the memory cells is amplified by the 512 sense amplifiers 2 and then, rewritten into each of the memory cells. More specifically, in one memory cycle, the 512 memory cells are refreshed. In such a refresh operation, the data signal as read out need not be outputted, so that the column address signal need not be applied.
Such a CAS before RAS refresh cycle of the RAS and CAS signals is repeated 512 times, so that the address counter 103 is incremented 512 times. Thus, the 512 word lines (WL1 to WL512 shown in FIG. 13A) are sequentially activated, so that all 256K-bit memory cells are refreshed. Thus, since four memory arrays are provided, a total of 1-megabit memory cells are all refreshed.
In general, it is determined that in the DRAM, the refresh operation is performed for each 16.mu.s on average. More specifically, in a case of 1-megabit DRAM, it is determined in the standard that the refresh operation is performed within about 16.mu.s.times.512 cycles=about 8ms, which is generally referred to as a refresh time. For reference, following are discussions of the refresh time for each storage capacity. More specifically, the refresh time is 16.mu.s.times.128=2ms in a 64k-bit DRAM, 16.mu.s.times.256=4ms in a 256K-bit DRAM, and 16.mu.s.times.1024=16ms in a 4-megabit DRAM. It is determined that the refresh cycle and the refresh time are increased by two times every time the storage capacity becomes four times.
If and when the DRAM is employed in an equipment having the above described battery backup function, the DRAM continues to be brought to a standby state at the time of backup of a battery. Thus, the refresh operation must be performed every constant time interval. In order to perform the refresh operation in the above described ordinary refresh mode, the RAS and CAS signals must be controlled (toggled) every one cycle, to be applied. In order to perform the refresh operation in such an ordinary refresh mode at the time of battery backup, there must be provided a circuit for controlling timings of the RAS and CAS signals and outputting the same. Consequently, the size of the equipment becomes larger and power consumption is increased, which are not preferable.
In order to solve the problems, a DRAM having a self-refresh mode was published, which has been already commercially available. The self-refresh mode is described in, for example, an article by YAMADA et al., entitled "A 64K bit MOS Dynamic RAM is Auto/Self Refresh Functions", Journal of Institute of Electronics and Communication Engineers of Japan, Vol. J66-C, No. 1, Jan. 1983.
FIG. 14 is a block diagram showing one example of the conventional DRAM having the self-refresh mode. When a high level external RAS signal is applied (in a standby state) and an external refresh signal REF continuous to be held at a low level during a set time (a maximum of 16.mu.s) or more of a timer, designation of the self-refresh mode is detected by a circuit 91. A refresh control circuit 92 operates a timer 93 in response to this detection. The timer 93 outputs a signal to a refresh address counter 94 through a circuit 92 every a maximum of 16.mu.s. Output signals Q.sub.0 to Q.sub.6 from the counter 94 are applied to a row decoder 98 through an address switching circuit 95 and an address buffer 96. The row decoder 98 decodes the signals Q.sub.0 to Q.sub.6, to sequentially select word lines as in the above described ordinary refresh operation, thereby to refresh a data signal in a memory array 97. As long as the signal REF continues to be held at a low level, the refresh operation in the self-refresh mode is continued. More specifically, as in the ordinary refresh mode, the refresh operation of 128 cycles is performed every a maximum of 2ms determined in the standard of a 64K-bit DRAM, so that all memory cells are refreshed.
Thus, the self-refresh mode is the same as the above described CAS before RAS refresh mode except that increment of the address counter 94 is not controlled by a clock signal externally applied but automatically controlled every constant time period by the self-contained timer 93.
As described in the foregoing, since the conventional DRAM having the self-refresh mode can automatically initiate a periodical refresh operation by setting a mode, the adaptation of the conventional DRAM to the equipment having the battery backup function is suitable from a point of view of decreasing power consumption at the time of battery backup. However, the power consumption required for the self-refresh operation itself is the same as the power consumption required for the ordinary refresh operation, which is not suitable for the operation under battery backup.
FIG. 15 is a timing chart for explaining the ordinary refresh operation of the DRAM shown in FIG. 12. In the DRAM shown in FIG. 12, the four memory cell arrays 21 to 24 are simultaneously refreshed in the ordinary refresh operation. More specifically, the four row decoders 11 receive the word line driving signal WL, to simultaneously select sequentially the word lines in the memory arrays 21 to 24. At the same time, the sense amplifier in each of the memory cell arrays 21 to 24 is driven by the sense amplifier driving signal So. The same operation is performed in the self-refresh operation of the DRAM having the self-refresh mode.
In addition, since the memory cell has the capacitor Co having the structure shown in FIG. 13C as described above, the leak current is large. Thus, a refresh cycle can not be set long. More specifically, in the case of not only the ordinary refresh mode but also the self-refresh mode, the refresh operation must be performed at a time interval at which the data signal held in the capacitor Co is not lost. Since the refresh cycle is short under the self-refresh mode of battery backup, a large refresh power is consumed in the DRAM.
An example of the prior art of particular interest in the present invention is shown in Japanese Patent Laying-Open Gazette No. 26897/1988. In this example, a volatile semiconductor memory is disclosed in which the number of word lines selected in a refresh operation is smaller than that selected in a reading or writing operation.